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A field-programmable gate array FPGA is an integrated circuit designed to be configured by a customer or a designer after manufacturing — hence the term field-programmable. Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools. FPGAs contain an array of programmable logic blocks , and a hierarchy of reconfigurable interconnects allowing blocks to be wired together. Logic blocks can be configured to perform complex combinational functions , or act as simple logic gates like AND and XOR.
In most FPGAs, logic blocks also include memory elements , which may be simple flip-flops or more complete blocks of memory. FPGAs have a remarkable role in embedded system development due to their capability to start system software development simultaneously with hardware, enable system performance simulations at a very early phase of the development, and allow various system trials and design iterations before finalizing the system architecture.
However, programmable logic was hard-wired between logic gates. Altera was founded in and delivered the industry's first reprogrammable logic device in — the EP — which featured a quartz window in the package that allowed users to shine an ultra-violet lamp on the die to erase the EPROM cells that held the device configuration.
Xilinx co-founders Ross Freeman and Bernard Vonderschmitt invented the first commercially viable field-programmable gate array in — the XC In , the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer that would implement , reprogrammable gates.
Casselman was successful and a patent related to the system was issued in Altera and Xilinx continued unchallenged and quickly grew from to the mids when competitors sprouted up, eroding a significant portion of their market share. By , Actel now Microsemi was serving about 18 percent of the market. The s were a period of rapid growth for FPGAs, both in circuit sophistication and the volume of production.
In the early s, FPGAs were primarily used in telecommunications and networking. By the end of the decade, FPGAs found their way into consumer, automotive, and industrial applications. Companies like Microsoft have started to use FPGAs to accelerate high-performance, computationally intensive systems like the data centers that operate their Bing search engine , due to the performance per watt advantage FPGAs deliver. Floor planning enables resource allocation within FPGAs to meet these time constraints.
The ability to update the functionality after shipping, partial re-configuration of a portion of the design [19] and the low non-recurring engineering costs relative to an ASIC design notwithstanding the generally higher unit cost , offer advantages for many applications. Some FPGAs have analog features in addition to digital functions.
The most common analog feature is a programmable slew rate on each output pin, allowing the engineer to set low rates on lightly loaded pins that would otherwise ring or couple unacceptably, and to set higher rates on heavily loaded pins on high-speed channels that would otherwise run too slowly. Fairly common are differential comparators on input pins designed to be connected to differential signaling channels. For example, a crossbar switch requires much more routing than a systolic array with the same gate count.
This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs. These might be split into two 3-input LUTs. In normal mode those are combined into a 4-input LUT through the first multiplexer mux.
In arithmetic mode, their outputs are fed to the adder. The selection of mode is programmed into the second mux. The output can be either synchronous or asynchronous , depending on the programming of the third mux. In practice, entire or parts of the adder are stored as functions into the LUTs in order to save space. Modern FPGA families expand upon the above capabilities to include higher level functionality fixed in silicon.
Having these common functions embedded in the circuit reduces the area required and gives those functions increased speed compared to building them from logical primitives.
These cores exist alongside the programmable fabric, but they are built out of transistors instead of LUTs so they have ASIC-level performance and power consumption without consuming a significant amount of fabric resources, leaving more of the fabric free for the application-specific logic. The multi-gigabit transceivers also contain high performance analog input and output circuitry along with high-speed serializers and deserializers, components which cannot be built out of LUTs.
Higher-level physical layer PHY functionality such as line coding may or may not be implemented alongside the serializers and deserializers in hard logic, depending on the FPGA.
An alternate approach to using hard-macro processors is to make use of soft processor IP cores that are implemented within the FPGA logic. Many modern FPGAs are programmed at "run time", which has led to the idea of reconfigurable computing or reconfigurable systems — CPUs that reconfigure themselves to suit the task at hand.
Additionally, new, non-FPGA architectures are beginning to emerge. Software-configurable microprocessors such as the Stretch S adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip. In the coarse-grained architectural approach was taken a step further by combining the logic blocks and interconnects of traditional FPGAs with embedded microprocessors and related peripherals to form a complete " system on a programmable chip ".
Most of the circuitry built inside of an FPGA is synchronous circuitry that requires a clock signal. FPGAs contain dedicated global and regional routing networks for clock and reset so they can be delivered with minimal skew. Complex designs can use multiple clocks with different frequency and phase relationships, each forming separate clock domains. These clock signals can be generated locally by an oscillator or they can be recovered from a high speed serial data stream.
Care must be taken when building clock domain crossing circuitry to avoid metastability. Xilinx's approach stacks several three or four active FPGA dies side by side on a silicon interposer — a single piece of silicon that carries passive interconnect. The HDL form is more suited to work with large structures because it's possible to specify high-level functional behavior rather than drawing every piece by hand.
However, schematic entry can allow for easier visualization of a design and its component modules. Using an electronic design automation tool, a technology-mapped netlist is generated. The netlist can then be fit to the actual FPGA architecture using a process called place-and-route , usually performed by the FPGA company's proprietary place-and-route software.
The user will validate the map, place and route results via timing analysis , simulation , and other verification and validation methodologies. Once the design and validation process is complete, the binary file generated, typically using the FPGA vendor's proprietary software, is used to re- configure the FPGA. However, in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages , there are moves [ by whom?
Verilog was created to simplify the process making HDL more robust and flexible. Verilog is currently the most popular. Verilog creates a level of abstraction to hide away the details of its implementation. To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. They are rarely free, and typically released under proprietary licenses.
Other predefined circuits are available from developer communities such as OpenCores typically released under free and open source licenses such as the GPL , BSD or similar license , and other sources.
Such designs are known as " open-source hardware. In a typical design flow , an FPGA application developer will simulate the design at multiple stages throughout the design process. Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate-level description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist.
These FPGAs are in-system programmable and re-programmable, but require external boot devices. In March , Tabula announced their FPGA technology that uses time-multiplexed logic and interconnect that claims potential cost savings for high-density applications. An FPGA can be used to solve any problem which is computable. Their advantage lies in that they are significantly faster for some applications because of their parallel nature and optimality in terms of the number of gates used for certain processes.
As their size, capabilities, and speed increased, FPGAs took over additional functions to the point where some are now marketed as full systems on chips SoCs. Particularly with the introduction of dedicated multipliers into FPGA architectures in the late s, applications which had traditionally been the sole reserve of digital signal processor hardware DSPs began to incorporate FPGAs instead.
Traditionally, [ when? For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC.
As of [update] , new cost and performance dynamics have broadened the range of viable applications. This device allows people to use computer RAM as a hard drive. FPGAs' flexibility makes malicious modifications during fabrication a lower risk. All major FPGA vendors now offer a spectrum of security solutions to designers such as bitstream encryption and authentication. For example, Altera and Xilinx offer AES encryption up to bit for bitstreams stored in an external flash memory.
FPGAs that store their configuration internally in nonvolatile flash memory, such as Microsemi 's ProAsic 3 or Lattice 's XP2 programmable devices, do not expose the bitstream and do not need encryption. In addition, flash memory for a lookup table provides single event upset protection for space applications.
A study from showed that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and run at one third the speed of corresponding ASIC implementations. Vendors can also take a middle road via FPGA prototyping : developing their prototype hardware on FPGAs, but manufacture their final version as an ASIC so that it can no longer be modified after the design has been committed. This is often also the case with new processor designs.
A CPLD has a comparatively restrictive structure consisting of one or more programmable sum-of-products logic arrays feeding a relatively small number of clocked registers. As a result, CPLDs are less flexible, but have the advantage of more predictable timing delays and a higher logic-to-interconnect ratio. This makes them far more flexible in terms of the range of designs that are practical for implementation on them but also far more complex to design for, or at least requiring more complex electronic design automation EDA software.
Another common distinction is that CPLDs contain embedded flash memory to store their configuration while FPGAs usually require external non-volatile memory but not always. When a design requires simple instant-on logic is already configured at power-up CPLDs are generally preferred. For most other applications FPGAs are generally preferred. In those designs, CPLDs generally perform glue logic functions, and are responsible for " booting " the FPGA as well as controlling reset and boot sequence of the complete circuit board.
From Wikipedia, the free encyclopedia. Array of logic gates that are reprogrammable. Not to be confused with Flip-chip pin grid array. Main article: Logic block. This section needs additional citations for verification. Please help improve this article by adding citations to reliable sources.
Unsourced material may be challenged and removed. June Learn how and when to remove this template message. Further information: Logic synthesis , Verification and validation , and Place and route. See also: Hardware acceleration. Electronics portal.
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